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1997 data sheet description a stricter quality assurance program (called special grade in necs grade classification) is applied to the m pd78052(a), 78053(a), and 78054(a), compared to the m pd78052, 78053, and 78054, which are classified as standard grade. the m pd78052(a), 78053(a), and 78054(a) belong to the m pd78054 subseries products of the 78k/0 series. these microcontrollers include the rich peripheral hardware, such as 8-bit resolution a/d converter, 8-bit resolution d/a converter, timer, serial interface, real-time output port, and interrupt functions. various development tools are also available. details of the function description, etc., are described in the following users manuals. be sure to read the documents when designing. m pd78054, 78054y subseries user's manual : u11747e 78k/0 series users manual instructions : ieu-1372 features ? large on-chip rom and ram item program memory data memory package (rom) m pd78052(a) 16 kbytes 512 bytes 32 bytes ? 80-pin plastic qfp (14 14 mm) m pd78053(a) 24 kbytes 1024 bytes m pd78054(a) 32 kbytes ? external memory expansion space: 64 kbytes ? instruction execution time can be varied from high-speed (0.4 m s) to ultra-low-speed (122 m s) ? i/o ports: 69 (n-ch open-drain : 4) ? 8-bit resolution a/d converter : 8 channels ? 8-bit resolution d/a converter : 2 channels ? serial interface : 3 channels ? timer: 5 channels ? power supply voltage : v dd = 2.0 to 6.0 v applications control devices of transport system, gas detector circuit-breakers, safety devices, etc. mos integrated circuit 8-bit single-chip microcontroller m pd78052(a), 78053(a), 78054(a) the information in this document is subject to change without notice. document no. u12171ej1v0ds00 (1st edition) date published march 1997 n printed in japan part number internal high- speed ram buffer ram
2 m pd78052(a), 78053(a), 78054(a) ordering information part number package quality grade m pd78052gc(a)- -3b9 80-pin plastic qfp (14 14 mm) special m pd78053gc(a)- -3b9 80-pin plastic qfp (14 14 mm) special m pd78054gc(a)- -3b9 80-pin plastic qfp (14 14 mm) special remark indicates rom code suffix. please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. differences between m pd78052(a), 78053(a), 78054(a) and standard products ( m pd78052, 78053, 78054) part number m pd78052(a), 78053(a), 78054(a) m pd78052, 78053, 78054 item package ? 80-pin plastic qfp (14 14 mm) ? 80-pin plastic qfp (14 14 mm) ? 80-pin plastic tqfp (fine pitch (12 12 mm)) quality grade special standard
3 m pd78052(a), 78053(a), 78054(a) 78k/0 series product development these products are a further development in the 78k/0 series. the designations appearing inside the boxes are subseries names. note under planning pd78014 pd78002 pd78083 pd78002y 100-pin 100-pin 100-pin 64-pin 64-pin 64-pin 42/44-pin control y subseries products are compatible with i 2 c bus. a timer was added to the pd78054, and external interface function was enhanced emi noise reduction version of the pd78078 rom-less versions of the pd78078 an a/d converter and 16-bit timer were added to the pd78002 an a/d converter was added to the pd78002 basic subseries for control on-chip uart, capable of operating at a low voltage (1.8 v) pd780018 note pd780018y note 100-pin serial i/o of the pd78078 was enhanced, and only selected functions are provided pd78078 pd78070a pd78075b pd78070ay m m mm mm mm m mm m m m m m m m inverter control pd780964 64-pin m an a/d converter of the pd780924 was enhanced pd78078y m m pd78075by pd78018f pd780001 pd78018fy pd78014y 80-pin 80-pin 64-pin 78k/0 series products in mass production products under development emi noise reduction version of the pd78054 uart and d/a converter were added to the pd78014, and i/o was enhanced low-voltage (1.8 v) operation versions of the pd78014 with several rom and ram capacities are available an a/d converter of the pd780024 was enhanced emi noise reduction version of the pd78018f on-chip inverter control circuit and uart, emi noise reduction version serial i/o of the pd78018f was enhanced, emi noise reduction version serial i/o of the pd78054 was enhanced, emi noise reduction version pd780058 80-pin m mm pd780034 pd780024 pd78014h pd780034y pd780024y 64-pin 64-pin 64-pin mm mm m m m m m m m m m fip tm drive pd78044f 100-pin 80-pin 80-pin m m the i/o and fip c/d of the pd78044f were enhanced, display output total: 53 the i/o and fip c/d of the pd78044h were enhanced, display output total: 48 n-ch open-drain input/output was added to the pd78044f, display output total: 34 basic subseries for driving fip, display output total: 34 m m 100-pin pd780924 64-pin m pd780308 pd78064b pd78064 100-pin 100-pin 100-pin m m sio of the pd78064 was enhanced, and rom and ram were expanded emi noise reduction version of the pd78064 subseries for driving lcds, on-chip uart m pd780308y m pd78064y m lcd drive m m iebus tm supported lv pd78098 80-pin m the iebus controller was added to the pd78054 m pd78p0914 64-pin m on-chip pwm output, lv digital code decoder, hsync counter pd78054 m pd78054y m pd78058fy m pd780058y note m pd78058f m pd78044h m m pd780228 pd780208 m
4 m pd78052(a), 78053(a), 78054(a) the major functional differences among the subseries are shown below. function rom timer 8-bit 10-bit 8-bit serial interface i/o v dd external subseries name capacity 8-bit 16-bit watch wdt a/d a/d d/a value expansion control m pd78075b 32 k-40 k 4ch 1ch 1ch 1ch 8ch C 2ch 3ch (uart: 1ch) 88 1.8 v available m pd78078 48 k-60 k m pd78070a C 61 2.7 v m pd780018 48 k-60 k C 2ch (time-division 3-wire:1ch) 88 m pd780058 24 k-60 k 2ch 2ch 3ch (time-division uart: 1ch) 68 1.8 v m pd78058f 48 k-60 k 3ch (uart: 1ch) 69 2.7 v m pd78054 16 k-60 k 2.0 v m pd780034 8 k-32 k C 8ch C 3ch (uart: 1ch, 51 1.8 v m pd780024 8ch C time-division 3-wire: 1ch) m pd78014h 2ch 53 m pd78018f 8 k-60 k m pd78014 8 k-32 k 2.7 v m pd780001 8 k C C 1ch 39 C m pd78002 8 k-16 k 1ch C 53 available m pd78083 C 8ch 1ch (uart: 1ch) 33 1.8 v C inverter m pd780964 8 k-32 k 3ch note C 1ch C 8ch C 2ch (uart: 2ch) 47 2.7 v available control m pd780924 8ch C fip m pd780208 32 k-60 k 2ch 1ch 1ch 1ch 8ch C C 2ch 74 2.7 v C drive m pd780228 48 k-60 k 3ch C C 1ch 72 4.5 v m pd78044h 32 k-48 k 2ch 1ch 1ch 68 2.7 v m pd78044f 16 k-40 k 2ch lcd m pd780308 48 k-60 k 2ch 1ch 1ch 1ch 8ch C C 3ch (time-division uart: 1ch) 57 2.0 v C drive m pd78064b 32 k 2ch (uart: 1ch) 2.0 v m pd78064 16 k-32 k iebus m pd78098 32 k-60 k 2ch 1ch 1ch 1ch 8ch C 2ch 3ch (uart: 1ch) 69 2.7 v available supported lv m pd78p0914 32 k 6ch C C 1ch 8ch C C 2ch 54 4.5 v available note 10-bit timer: 1 channel min.
5 m pd78052(a), 78053(a), 78054(a) memory space general registers instruction cycle instruction set i/o ports a/d converter d/a converter timer timer output clock output buzzer output v dd = 2.0 to 6.0 v t a = C40 to +85 c ? 80-pin plastic qfp (14 14 mm) 16 kbytes 24 kbytes 32 kbytes 512 bytes 1024 bytes 32 bytes 64 kbytes 8 bits 32 registers (8 bits 8 registers 4 banks) on-chip instruction execution time cycle modification function 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s/12.8 m s (at 5.0-mhz operation) 122 m s (at 32.768-khz operation) ? 16-bit operation ? multiplication/division (8 bits 8 bits,16 bits ? 8 bits) ? bit manipulation (set, reset, test, boolean operation) ? bcd adjustment, etc. total : 69 ? cmos input : 0 2 ? cmos i/o : 63 ? n-ch open-drain i/o : 0 4 8-bit resolution 8 channels 8-bit resolution 2 channels ? 3-wire serial i/o, sbi, or 2-wire serial i/o mode selectable: 1 channel ? 3-wire serial i/o mode (on-chip max. 32 bytes automatic transmit/receive function): 1 channel ? 3-wire serial i/o or uart mode selectable: 1 channel ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel 3 (14-bit pwm output 1) 19.5 khz, 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz, 2.5 mhz, 5.0 mhz (at main system clock 5.0-mhz operation) 32.768 khz (at subsystem clock 32.768-khz operation) 1.2 khz, 2.4 khz, 4.9 khz, 9.8 khz (at main system clock 5.0-mhz operation) internal : 13, external : 7 internal : 1 1 internal : 1, external : 1 function overview part number item m pd78052(a) m pd78053(a) m pd78054(a) when main system clock selected when subsystem clock selected serial interface internal memory rom high-speed ram buffer ram vectored interrupt source maskable non-maskable software test input power supply voltage operating ambient temperature package
6 m pd78052(a), 78053(a), 78054(a) contents 1. pin configuration (top view) ................................................................................................................. 7 2. block diagram .......................................................................................................................................... 9 3 pin functions ............................................................................................................................................. 10 3.1 port pins ................................................................................................................................................. 10 3.2 non-port pins ........................................................................................................................................ 12 3.3 pin i/o circuits and recommended connection of unused pins ................................................. 14 4. memory space ............................................................................................................................................. 18 5. peripheral hardware function features ................................................................................... 19 5.1 ports ........................................................................................................................................................ 19 5.2 clock generator .................................................................................................................................... 20 5.3 timer/event counter ............................................................................................................................. 20 5.4 clock output control circuit ............................................................................................................... 23 5.5 buzzer output control circuit ............................................................................................................ 23 5.6 a/d converter ........................................................................................................................................ 24 5.7 d/a converter ........................................................................................................................................ 25 5.8 serial interfaces .................................................................................................................................... 25 5.9 real-time output port .......................................................................................................................... 27 6. interrupt functions and test functions ..................................................................................... 28 6.1 interrupt functions ............................................................................................................................... 28 6.2 test functions ....................................................................................................................................... 32 7. external device expansion functions ........................................................................................... 33 8. standby function ..................................................................................................................................... 33 9. reset function ........................................................................................................................................... 33 10. instruction set .......................................................................................................................................... 34 11. electrical specifications .................................................................................................................... 37 12. characteristic curves (for reference only) ............................................................................ 65 13. package drawing ...................................................................................................................................... 67 14. recommended soldering conditions .............................................................................................. 68 appendix a. development tools ............................................................................................................. 69 appendix b. related documents ............................................................................................................ 71
7 m pd78052(a), 78053(a), 78054(a) m 1. pin configuration (top view) ? 80-pin plastic qfp (14 14 mm) m pd78052gc(a)- -3b9 m pd78053gc(a)- -3b9 m pd78054gc(a)- -3b9 cautions 1. connect directly the ic (internally connected) pin to v ss . 2. connect the av dd pin to v dd . 3. connect the av ss pin to v ss . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 p15/ani5 p16/ani6 p17/ani7 av ss p130/ano0 p131/ano1 av ref1 p70/si2/rxd p71/so2/txd p72/sck2/asck p20/si1 p21/so1 p22/sck1 p23/stb p24/busy p25/si0/sb0 p26/so0/sb1 p27/sck0 p40/ad0 p41/ad1 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 p47/ad7 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 v ss p56/a14 p57/a15 p60 p61 p62 p63 p64/rd 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 reset p127/rtp7 p126/rtp6 p125/rtp5 p124/rtp4 p123/rtp3 p122/rtp2 p121/rtp1 p120/rtp0 p37 p36/buz p35/pcl p34/ti2 p33/ti1 p32/to2 p31/to1 p30/to0 p67/astb p66/wait p65/wr 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 p14/ani4 p13/ani3 p12/ani2 p11/ani1 p10/ani0 av ref0 av dd xt1/p07 xt2 ic x1 x2 v dd p06/intp6 p05/intp5 p04/intp4 p03/intp3 p02/intp2 p01/intp1/ti01 p00/intp0/ti00
8 m pd78052(a), 78053(a), 78054(a) pcl : programmable clock rd : read strobe reset : reset rtp0-rtp7 : real-time output port rxd : receive data sb0, sb1 : serial bus sck0-sck2 : serial clock si0-si2 : serial input so0-so2 : serial output stb : strobe ti00, ti01 : timer input ti1, ti2 : timer input to0-to2 : timer output txd : transmit data v dd : power supply v ss : ground wait : wait wr : write strobe x1, x2 : crystal (main system clock) xt1, xt2 : crystal (subsystem clock) a8-a15 : address bus ad0-ad7 : address/data bus ani0-ani7 : analog input ano0, ano1 : analog output asck : asynchronous serial clock astb : address strobe av dd : analog power supply av ref0 , av ref1 : analog reference voltage av ss : analog ground busy : busy buz : buzzer clock ic : internally connected intp0-intp6 : interrupt from peripherals p00-p07 : port0 p10-p17 : port1 p20-p27 : port2 p30-p37 : port3 p40-p47 : port4 p50-p57 : port5 p60-p67 : port6 p70-p72 : port7 p120-p127 : port12 p130, p131 : port13
9 m pd78052(a), 78053(a), 78054(a) 2. block diagram remark the internal rom and ram capacity depends on the product. to0/p30 ti00/intp0/p00 ti01/intp1/p01 16-bit timer/ event counter to1/p31 ti1/p33 8-bit timer/ event counter 1 to2/p32 ti2/p34 8-bit timer/ event counter 2 watchdog timer watch timer serial interface 0 si0/sb0/p25 so0/sb1/p26 sck0/p27 si1/p20 so1/p21 sck1/p22 stb/p23 busy/p24 serial interface 1 si2/rxd/p70 so2/txd/p71 sck2/asck/p72 ani0/p10- ani7/p17 av ref0 av ss av dd ano0/p130, ano1/p131 av ref1 av ss intp0/p00- intp6/p06 buz/p36 pcl/p35 serial interface 2 a/d converter d/a converter interrupt control buzzer output clock output control port0 port1 port2 port3 port4 port5 port6 port7 port12 port13 real-time output port external access system control v dd v ss ic 78k/0 cpu core rom ram p00 p01-p06 p07 p10-p17 p20-p27 p30-p37 p40-p47 p50-p57 p60-p67 p70-p72 p120-p127 p130, p131 rtp0/p120- rtp7/p127 ad0/p40- ad7/p47 a8/p50- a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 reset x1 x2 xt1/p07 xt2
10 m pd78052(a), 78053(a), 78054(a) 3. pin functions 3.1 port pins (1/2) dual- function pin pin name i/o input only input input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used by software. input/ output input only port 1 8-bit input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used by software. note 2 input/ output input/ output port 2 8-bit input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used by software. port 3 8-bit input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used by software. input/ output input/ output port 4 8-bit input/output port. input/output can be specified in 8-bit unit. when used as an input port, on-chip pull-up resistor can be used by software. test input flag (krif) is set to 1 by falling edge detection. intp0/ti00 intp1/ti01 intp2 intp3 intp4 intp5 intp6 xt1 ani0 to ani7 si1 so1 sck1 stb busy si0/sb0 so0/sb1 sck0 to0 to1 to2 ti1 ti2 pcl buz ad0 to ad7 p00 p01 p02 p03 p04 p05 p06 p07 note 1 p10 to p17 p20 p21 p22 p23 p24 p25 p26 p27 p30 p31 p32 p33 p34 p35 p36 p37 p40 to p47 input function port 0 8-bit i/o port input input after reset input input input input input notes 1. when using the p07/xt1 pin as an input port, set 1 in the bit 6 (frc) of the processor clock control register (pcc). on-chip feedback resistor of the subsystem clock oscillator should not be used. 2. when using the p10/ani0 to p17/ani7 pins as the a/d converter analog input pins, use of the pull-up resistor is cancelled automatically.
11 m pd78052(a), 78053(a), 78054(a) 3.1 port pins (2/2) dual- function pin function pin name i/o input/ output input/ output p50 to p57 when used as an input port, on-chip pull-up resistor can be used by software. p60 p61 p62 p63 p64 p65 p66 p67 p70 p71 p72 p120 to p127 p130, p131 input/ output input/ output input/ output n-ch open-drain input/output port. on-chip pull-up resistor can be specified by mask option. led can be driven directly. after reset port 5 8-bit input/output port. led can be driven directly. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used by software. port 6 8-bit input/outport port. input/output can be specified bit-wise. port 13 2-bit input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used by software. port 12 8-bit input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used by software. port 7 3-bit input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used by software. input input input input input input a8 to a15 rd wr wait astb si2/rxd so2/txd sck2/asck rtp0 to rtp7 ano0, ano1
12 m pd78052(a), 78053(a), 78054(a) p00/ti00 p01/ti01 p02 p03 p04 p05 p06 p25/sb0 p20 p70/rxd p26/sb1 p21 p71/txd p25/si0 p26/so0 p27 p22 p72/asck p23 p24 p70/si2 p71/so2 p72/sck2 p00/intp0 p01/intp1 p33 p34 p30 p31 p32 p35 p36 p120 to p127 p40 to p47 p50 to p57 p64 p65 dual- function pin function pin name i/o input external interrupt input by which the effective edge (rising edge, falling edge, or both rising edge and falling edge) can be specified. input serial interface serial data input. output serial interface serial data output. serial interface serial data input/output. input/ output input/ output serial interface serial clock input/output. serial interface automatic transmit/receive strobe output. serial interface automatic transmit/receive busy input. output input input output output input input output asynchronous serial interface serial data input. asynchronous serial interface serial data output. 3.2 non-port pins (1/2) output intp0 intp1 intp2 intp3 intp4 intp5 intp6 si0 si1 si2 so0 so1 so2 sb0 sb1 sck0 sck1 sck2 stb busy rxd txd asck ti00 ti01 ti1 ti2 to0 to1 to2 pcl buz rtp0 to rtp7 ad0 to ad7 a8 to a15 rd wr output clock output (for main system clock, subsystem clock trimming). buzzer output. real-time output port by which data is output in synchronization with a trigger. low-order address/data bus at external memory expansion. high-order address bus at external memory expansion. external memory read operation strobe signal output. external memory write operation strobe signal output. input/ output output output after reset input input input input input input input input input input input input input input input input input input external count clock input to 16-bit timer (tm0). asynchronous serial interface serial clock input. capture trigger signal input to capture register (cr00). external count clock input to 8-bit timer (tm1). external count clock input to 8-bit timer (tm2). 16-bit timer (tm0) output (dual-function as 14-bit pwm output). 8-bit timer (tm1) output. 8-bit timer (tm2) output.
13 m pd78052(a), 78053(a), 78054(a) p66 p67 p10 to p17 p130, p131 p07 3.2 non-port pins (2/2) dual- function pin function pin name i/o input output input output input input input input input wait astb ani0 to ani7 ano0, ano1 av ref0 av ref1 av dd av ss reset x1 x2 xt1 xt2 v dd v ss ic wait insertion at external memory access. strobe output which latches the address information output at port 4 and port 5 to access external memory. a/d converter analog input. d/a converter analog output. a/d converter reference voltage input. d/a converter reference voltage input. a/d converter analog power supply. connect to v dd . a/d and d/a converter ground potential. connect to v ss . system reset input. main system clock oscillation crystal connection. subsystem clock oscillation crystal connection. positive power supply. ground potential. internal connection. connect to v ss directly. after reset input input input input input
14 m pd78052(a), 78053(a), 78054(a) p00/intp0/ti00 p01/intp1/ti01 p02/intp2 p03/intp3 p04/intp4 p05/intp5 p06/intp6 p07/xt1 p10/ani0 to p17/ani7 p20/si1 p21/so1 p22/sck1 p23/stb p24/busy p25/si0/sb0 p26/so0/sb1 p27/sck0 p30/to0 p31/to1 p32/to2 p33/ti1 p34/ti2 p35/pcl p36/buz p37 p40/ad0 to p47/ad7 p50/a8 to p57/a15 p60 to p63 p64/rd p65/wr p66/wait p67/astb 3.3 pin i/o circuits and recommended connection of unused pins the input/output circuit type of each pin and recommended connection of unused pins are shown in table 3-1. for the input/output circuit configuration of each type, see figure 3-1. table 3-1. input/output circuit type of each pin (1/2) input/output circuit type 2 8-a 16 11 8-a 5-a 8-a 5-a 8-a 10-a 5-a 8-a 5-a 5-e 5-a 13-b 5-a input input/output input input/output connect to v ss . connect to v ss via a resistor individually. connect to v dd . pin name i/o recommended connection when not used connect to v dd or v ss via a resistor individually. connect to v dd via a resistor individually. connect to v dd or v ss via a resistor individually. connect to v dd via a resistor individually. connect to v dd or v ss via a resistor individually.
15 m pd78052(a), 78053(a), 78054(a) connect to v dd or v ss via a resistor individually. connect to v ss via a resistor individually. leave open. connect to v ss . connect to v dd . table 3-1. input/output circuit type of each pin (2/2) input/output circuit type p70/si2/rxd p71/so2/txd p72/sck2/asck p120/rtp0 to p127/rtp7 p130/ano0, p131/ano1 reset xt2 av ref0 av ref1 pin name i/o recommended connection when not used 8-a 5-a 8-a 5-a 12-a 2 16 input/ output input av dd av ss ic connect to v ss . connect to v ss directly.
16 m pd78052(a), 78053(a), 78054(a) figure 3-1. pin input/output circuits (1/2) type 2 in type 8-a pullup enable data output disable v p-ch n-ch p-ch in/out dd v dd type 10-a enable type 11 pullup enable data output disable p-ch n-ch p-ch in/out v dd type 5-a input enable type 5-e pullup enable data output disable v p-ch n-ch p-ch in/out dd v dd schmitt-triggered input with hysteresis characteristic pullup enable data output disable in/out v ref input dd (threshold voltage) v p-ch n-ch p-ch dd v p-ch + - comparator pullup enable data output disable v p-ch n-ch p-ch in/out dd v dd open drain v dd n-ch
17 m pd78052(a), 78053(a), 78054(a) figure 3-1. pin input/output circuits (2/2) type 12-a type 16 pullup enable data output disable v p-ch n-ch p-ch in/out dd v dd n-ch input enable type 13-b data output disable n-ch p-ch in/out v dd v dd rd mask option middle-high voltage input buffer p-ch analog output voltage xt1 feedback cut-off xt2 p-ch
18 m pd78052(a), 78053(a), 78054(a) 4. memory space figure 4-1 shows the m pd78052(a), 78053(a), 78054(a) memory map. figure 4-1. memory map note the internal rom capacity and internal high-speed ram capacity depend on the products (see the following table). internal rom last address nnnnh relevant product name 3fffh m pd78052(a) m pd78053(a) 5fffh internal high-speed ram start address mmmmh fd00h fb00h m pd78054(a) 7fffh special function registers (sfr) 256 8 bits general registers 32 8 bits internal high-speed ram note use prohibited buffer ram 32 8 bits use prohibited external memory internal rom note data memory space program memory space ffffh ff00h feffh fee0h fedfh mmmmh mmmmh ?1 fae0h fadfh fac0h fabfh fa80h fa7fh nnnnh + 1 nnnnh 0000h program area callf entry area program area callt table area vector table area nnnnh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h
19 m pd78052(a), 78053(a), 78054(a) 5. peripheral hardware function features 5.1 ports the following 3 types of i/o ports are available. ? cmos input (p00, p07) :2 ? cmos input/output (p01 to p06, port 1 to port 5, p64 to p67, port 7, port 12, port 13) : 63 ? n-channel open-drain input/output (p60 to p63) : 4 total : 69 table 5-1. port functions pin name function dedicated input port pins input/output port pins. input/output specifiable bit-wise. when used as input port pins, on-chip pull-up resistor can be used by software. input/output port pins. input/output specifiable bit-wise. when used as input port pins, on-chip pull-up resistor can be used by software. input/output port pins. input/output specifiable bit-wise. when used as input port pins, on-chip pull-up resistor can be used by software. input/output port pins. input/output specifiable bit-wise. when used as input port pins, on-chip pull-up resistor can be used by software. input/output port pins. input/output specifiable in 8-bit units. when used as input port pins, on-chip pull-up resistor can be used by software. test input flag (krif) is set to 1 by falling edge detection. input/output port pins. input/output specifiable bit-wise. when used as input port pins, on-chip pull-up resistor can be used by software. led direct drive capability. n-channel open-drain input/output port pins. input/output specifiable bit-wise. on-chip pull-up resistor can be used by mask option. led direct drive capability. input/output port pins. input/output specifiable bit-wise. when used as input port pins, on-chip pull-up resistor can be used by software. input/output port pins. input/output specifiable bit-wise. when used as input port pins, on-chip pull-up resistor can be used by software. input/output port pins. input/output specifiable bit-wise. when used as input port pins, on-chip pull-up resistor can be used by software. input/output port pins. input/output specifiable bit-wise. when used as input port pins, on-chip pull-up resistor can be used by software. name port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 port 12 port 13 p10 to p17 p20 to p27 p30 to p37 p40 to p47 p50 to p57 p60 to p63 p64 to p67 p70 to p72 p120 to p127 p130, p131 p00, p07 p01 to p06
20 m pd78052(a), 78053(a), 78054(a) 5.2 clock generator two types of generators, a main system clock generator and a subsystem clock generator, are available. the instruction execution time can also be changed. ? 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s/12.8 m s (main system clock: at 5.0-mhz operation) ? 122 m s (subsystem clock: at 32.768-khz operation) figure 5-1. clock generator block diagram 16-bit timer/event counter 8-bit timer/event counter watch timer watchdog timer external event counter 2 channels type timer output pwm output square wave output 1 output 1 output 2 inputs pulse width measurement 2 outputs interrupt source 21 1 2 function 1 channel 1 channel 2 channels 1 channel interval timer 1 channel 1 output 2 outputs one-shot pulse output 1 output test input 1 input 5.3 timer/event counter the m pd78052(a), 78053(a), and 78054(a) incorporate 5 channels of the timer/event counter. ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel table 5-2. types and functions of timer/event counter xt1/p07 xt2 x1 x2 f xt f xx subsystem clock oscillator watch timer, clock output function prescaler main system clock oscillator clock to peripheral hardware cpu clock (f cpu ) standby control circuit wait control circuit to intp0 sampling clock 2 f xx 2 2 f xx 2 3 f xx 2 4 f xx f xt 2 prescaler selector selector f x f x 2 stop divider 2 1
21 m pd78052(a), 78053(a), 78054(a) figure 5-2. 16-bit timer/event counter block diagram figure 5-3. 8-bit timer/event counter block diagram internal bus selector selector 16-bit timer register (tm0) clear output control circuit pwm pulse output control circuit 16-bit capture/ compare register internal bus intp1 inttm00 to0/p30 inttm01 intp0 ti01/p01/intp1 watch timer output 2f xx f xx f xx /2 2 f xx /2 ti00/p00/intp0 16-bit capture/ compare register (cr01) (cr00) edge detector match match selector internal bus 8-bit compare register (cr10) 8-bit timer register 1 (tm1) clear match selector output control circuit output control circuit inttm1 to2/p32 inttm2 to1/p31 clear match selector selector selector selector 8-bit compare register (cr20) 8-bit timer register 2 (tm2) internal bus f xx /2-f xx /2 f xx /2 9 11 ti1/p33 f xx /2-f xx /2 f xx /2 9 11 ti2/p34
22 m pd78052(a), 78053(a), 78054(a) figure 5-4. watch timer block diagram figure 5-5. watchdog timer block diagram inttm3 intwt 5-bit counter prescaler selector selector selector selector f xx /2 f xt 7 f w 2 f w 4 2 f w 5 2 f w 6 2 f w 7 2 f w 8 2 f w 9 2 f w 14 2 f w 13 to 16-bit timer/ event counter control circuit 8-bit counter prescaler intwdt non-maskable interrupt request intwdt maskable interrupt request reset selector 2 f xx 4 2 f xx 5 2 f xx 6 2 f xx 7 2 f xx 8 2 f xx 9 2 f xx 11 2 f xx 3
23 m pd78052(a), 78053(a), 78054(a) 5.4 clock output control circuit the clock with the following frequency can be output as a clock output. ? 19.5 khz/39.1 khz/78.1 khz/156 khz/313 khz/625 khz/1.25 mhz/2.5 mhz/5.0 mhz (main system clock: at 5.0- mhz operation) ? 32.768 khz (subsystem clock: at 32.768-khz operation) figure 5-6. clock output control circuit block diagram 5.5 buzzer output control circuit the clock with the following frequency can be output as a buzzer output. ? 1.2 khz/2.4 khz/4.9 khz/9.8 khz (main system clock: at 5.0-mhz operation) figure 5-7. buzzer output control circuit block diagram selector synchronization circuit output control circuit pcl/p35 f xx f xx f xx f xx f xx f xx /2 /2 2 /2 3 /2 4 /2 5 f xx /2 6 f xx f xt /2 7 selector output control circuit buz/p36 f xx /2 9 f xx /2 10 f xx /2 11
24 m pd78052(a), 78053(a), 78054(a) 5.6 a/d converter an a/d converter of 8-bit resolution 8 channels is incorporated. the following two types of the a/d conversion operation start-up methods are available. ? hardware start ? software start figure 5-8. a/d converter block diagram tap selector intad av dd intp3 internal bus av ref0 a/d conversion result register (adcr) control circuit succesive approximation register (sar) edge detection circuit ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 ani5/p15 ani6/p16 ani7/p17 intp3/p03 selector sample & hold circuit voltage comparator series resistor string av ss
25 m pd78052(a), 78053(a), 78054(a) n = 0, 1 m = 4, 5 x = 1, 2 5.8 serial interfaces 3 channels of the clocked serial interface are incorporated. ? serial interface channel 0 ? serial interface channel 1 ? serial interface channel 2 table 5-3. types and functions of serial interface 5.7 d/a converter a d/a converter of 8-bit resolution 2 channels is incorporated. conversion method is r-2r resistor ladder method. figure 5-9. d/a converter block diagram function 3-wire serial i/o mode with automatic transmit/ receive function sbi (serial bus interface) mode 2-wire serial i/o mode asynchronous serial interface (uart) mode 3-wire serial i/o mode ? (msb/lsb first switchable) ? (msb/lsb first switchable) ? (msb first) ? (msb first) ? (dedicated baud rate generator incorporated) serial interface channel 0 serial interface channel 1 serial interface channel 2 ? (msb/lsb first switchable) ? (msb/lsb first switchable) internal bus selector d/a conversion value set register n (dacsn) av ref1 av ss damm inttm x dacsn write anon d/a converter mode register
26 m pd78052(a), 78053(a), 78054(a) figure 5-10. serial interface channel 0 block diagram figure 5-11. serial interface channel 1 block diagram busy/acknowledge output circuit output latch serial i/o shift register 0 (sio0) internal bus interrupt request signal generator serial clock counter bus release/command/ acknowledge detection circuit serial clock control circuit selector selector selector si0/sb0/p25 so0/sb1/p26 sck0/p27 intcsi0 to2 f xx /2-f xx /2 8 internal bus interrupt request signal generator handshake control circuit buffer ram serial clock control circuit selector serial counter serial i/o shift register 1 (sio1) automatic data transmit/ receive address pointer (adtp) automatic data transmit/receive interval specification register (adti) 5-bit counter intcsi1 f xx /2-f xx /2 to2 8 si1/p20 so1/p21 stb/p23 busy/p24 sck1/p22 match
27 m pd78052(a), 78053(a), 78054(a) figure 5-12. serial interface channel 2 block diagram 5.9 real-time output port data set previously in the real-time output buffer register is transferred to the output latch by hardware concurrently with timer interrupt or external interrupt generation in order to output to off-chip. this is real-time output function. and pins to output to off-chip are called real-time output ports. by using a real-time output port, a signal which has no jitter can be output. this is most applicable to control of stepping motor, etc. figure 5-13. real-time output port block diagram rxd/si2/p70 txd/so2/p71 asck/sck2/p72 intser intsr/intcsi2 intst f xx -f xx /2 10 internal bus receive buffer register (rxb/sio2) direction control circuit receive shift register (rxs) receive control circuit direction control circuit transmit shift register (txs/sio2) transmit control circuit sck output control circuit baud rate generator internal bus p127 p120 output latch real-time output buffer register higher 4 bits (rtbh) real-time output buffer register lower 4 bits (rtbl) real-time output port mode register (rtpm) output trigger control circuit intp2 inttm1 inttm2
28 m pd78052(a), 78053(a), 78054(a) ? non-maskable : 1 ? maskable : 20 ? software : 1 note 1 default priority name watchdog timer overflow (watchdog timer mode 1 selected) interrupt source trigger watchdog timer overflow (interval timer mode selected) 1 2 3 4 5 6 7 intp0 intp1 intp2 intp3 intp4 intp5 intp6 0006h 0008h 000ah 000ch 000eh 0010h 0012h (c) end of serial interface channel 0 transfer internal/ external vector table address basic configuration type note 2 CCC intwdt non-maskable (a) internal 0004h 0 intwdt (b) pin input edge detection external maskable intcsi0 8 0014h (b) (d) 6. interrupt functions and test functions 6.1 interrupt functions there are 22 interrupt functions of three different kinds, as shown below. internal intcsi1 0016h 9 intser 10 0018h intst 12 end of serial interface channel 1 transfer table 6-1. interrupt source list (1/2) generation of serial interface channel 2 uart receive error 11 intsr 001ah end of serial interface channel 2 uart reception end of serial interface channel 2 3-wire transfer intcsi2 end of serial interface channel 2 uart transmission 001ch notes 1. the default priority is a priority order when two or more maskable interrupts are generated simultaneously. 0 is the highest order and 18, the lowest. 2. basic configuration types (a) to (e) correspond to (a) to (e) in figure 6-1, respectively. kind of interrupt
29 m pd78052(a), 78053(a), 78054(a) table 6-1. interrupt source list (2/2) name interrupt source reference time interval signal from watch timer generation of match signal of 16-bit timer register and capture/compare register (cr00) generation of match signal of 16-bit timer register and capture/compare register (cr01) generation of match signal of 8-bit timer/event counter 1 generation of match signal of 8-bit timer/ event counter 2 end of conversion by a/d converter brk instruction execution intad brk 0028h 003eh (e) notes 1. the default priority is a priority order when two or more maskable interrupts are generated simultaneously. 0 is the highest order and 18, the lowest. 2. basic configuration types (a) to (e) correspond to (a) to (e) in figure 6-1, respectively. kind of interrupt software 13 inttm3 001eh (b) internal/ external vector table address basic configuration type note 2 trigger 14 inttm00 0020h internal inttm01 15 0022h inttm1 16 0024h inttm2 17 0026h note 1 default priority maskable 18
30 m pd78052(a), 78053(a), 78054(a) figure 6-1. interrupt function basic configuration (1/2) (a) internal non-maskable interrupt (b) internal maskable interrupt (c) external maskable interrupt (intp0) mk internal bus ie pr isp if priority control circuit vector table address generator standby release signal interrupt request mk ie pr isp if priority control circuit vector table address generator sampling clock select register (scs) external interrupt mode register (intm0) edge detection circuit sampling clock internal bus standby release signal interrupt request internal bus priority control circuit vector table address generator standby release signal interrupt request
31 m pd78052(a), 78053(a), 78054(a) figure 6-1. interrupt function basic configuration (2/2) (d) external maskable interrupt (except intp0) (e) software interrupt if : interrupt request flag ie : interrupt enable flag isp : in-service priority flag mk : interrupt mask flag pr : priority specification flag mk ie pr isp if priority control circuit vector table address generator external interrupt mode register (intm0, intm1) edge detection circuit internal bus standby release signal interrupt request priority control circuit vector table address generator internal bus interrupt request
32 m pd78052(a), 78053(a), 78054(a) 6.2 test functions there are two test functions as shown in table 6-2. table 6-2. test input source list internal/external name intpt4 intwt watch timer overflow port 4 falling edge detection internal external test input source trigger figure 6-2. test function basic configuration if : test input flag mk : test mask flag mk internal bus if standby release signal test input
33 m pd78052(a), 78053(a), 78054(a) 7. external device expansion functions the external device expansion functions connect external devices to areas other than the internal rom, ram and sfr. ports 4 to 6 are used for external device connection. 8. standby function there are the following two standby functions to reduce the consumption current. ? halt mode : the cpu operating clock is stopped. the average consumption current can be reduced by intermittent operation in combination with the normal operating mode. ? stop mode : the main system clock oscillation is stopped. the whole operation by the main system clock is stopped, so that the system operates with ultra-low power consumption using only the subsystem clock. figure 8-1. standby function note the consumption current can be reduced by stopping the main system clock. when the cpu is operating on the subsystem clock, set bit 7 (mcc) in the processor clock control register (pcc) to stop the main system clock. the stop instruction cannot be used. 9. reset function there are the following two reset methods. ? external reset by reset pin ? internal reset by watchdog timer runaway time detection caution when the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program. remark css : bit 4 in the pcc main system clock operation stop mode (main system clock oscillation stopped) halt mode (clock supply to cpu is stopped, oscillation maintained) subsystem clock operation note halt mode note (clock supply to cpu is stopped, oscillation maintained) interrupt request interrupt request interrupt request halt instruction halt instruction stop instruction css = 1 css = 0
34 m pd78052(a), 78053(a), 78054(a) 10. instruction set (1) 8-bit instruction mov, xch, add addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz note except r = a second operand first operand #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + byte] [hl + b] [hl + c] $addr16 1 none a r add addc sub subc and or xor cmp mov mov mov mov mov mov mov mov ror xch xch xch xch xch xch xch rol add add add add add rorc addc addc addc addc addc rolc sub sub sub sub sub subc subc subc subc subc and and and and and or or or or or xor xor xor xor xor cmp cmp cmp cmp cmp mov mov add addc sub subc and or xor cmp inc dec b, c sfr mov mov dbnz mov add addc sub subc and or xor cmp saddr mov dbnz inc dec !addr16 mov psw mov mov push pop [de] ror4 mov [hl] mov rol4 [hl + byte] [hl + b] [hl + c] mov x c mulu divuw
35 m pd78052(a), 78053(a), 78054(a) (2) 16-bit instruction movw, xchw, addw, subw, cmpw, push, pop, incw, decw note only when rp = bc, de or hl (3) bit manipulation instruction mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr (4) call instruction/branch instruction call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz second operand first operand ax rp sfrp saddrp !addr16 sp #word addw subw cmpw movw movw movw movw ax movw note movw movw movw movw movw rp note xchw sfrp movw saddrp movw !addr16 movw sp movw none incw, decw push, pop second operand first operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none a.bit sfr.bit saddr.bit psw.bit [hl].bit cy mov1 mov1 mov1 mov1 mov1 bt bf btclr bt bf btclr bt bf btclr bt bf btclr bt bf btclr set1 clr1 set1 clr1 set1 clr1 set1 clr1 set1 clr1 set1 clr1 not1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 second operand first operand ax !addr16 !addr11 [addr5] $addr16 basic instruction compound instruction br call br callf callt br, bc, bnc bz, bnz bt, bf btclr dbnz
36 m pd78052(a), 78053(a), 78054(a) (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop
37 m pd78052(a), 78053(a), 78054(a) parameter symbol test conditions rating unit supply voltage v dd C0.3 to +7.0 v av dd C0.3 to v dd +0.3 v av ref0 C0.3 to v dd +0.3 v av ref1 C0.3 to v dd +0.3 v av ss C0.3 to +0.3 v input voltage v i1 p00 to p07, p10 to p17, p20 to p27, p30 top37, p40 to p47, C0.3 to v dd +0.3 v p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131, x1, x2, xt2, reset v i2 p60 to p63 n-ch open-drain C0.3 to +16 v output voltage v o C0.3 to v dd +0.3 v analog intput voltage v o p10 to p17 analog input pin av ss C0.3 to av ref0 +0.3 v high level output i oh 1 pin C10 ma current p01 to p06, p30-p37, p56, p57, p60 to p67, p120 to p127 total C15 ma p10 to p17, p20 to p27, p40 to p47, p50 to p55, C15 ma p70 to p72, p130, p131 total low level output i ol note 1 pin peak value 30 ma current effective value 15 ma p50 to p55 total peak value 100 ma effective value 70 ma p56, p57, p60 to p63 total peak value 100 ma effective value 70 ma p10 to p17, p20 to p27, p40 to p47, peak value 50 ma p70 to p72, p130, p131 total effective value 20 ma p01 to p06, p30 to p37, p64 to p67, peak value 50 ma p120 to p127 total effective value 20 ma operating ambient t a C40 to +85 c temperature storage t stg C65 to +150 c temperature 11. electrical specifications absolute maximum ratings (t a = 25 c) note effective value should be calculated as follows: [effective value] = [peak value] ? duty caution product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even momentarily. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. remark the characteristics of dual-function pins and port pins are the same unless otherwise specified.
38 m pd78052(a), 78053(a), 78054(a) main system clock oscillation circuit characteristics (t a = e40 to 85 c, v dd = 2.0 to 6.0 v) recommended circuit typ. max. 5.0 4 5.0 10 30 5.0 500 unit mhz ms mhz ms mhz ns resonator ceramic resonator crystal resonator external clock parameter oscillation frequency (f x ) note 1 oscillation stabilization time note 2 oscillation frequency (f x ) note 1 oscillation stabilization time note 2 x1 input frequency (f x ) note 1 x1 input high-/low-level width (t xh , t xl ) notes 1. indicates only oscillation circuit characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the main system clock oscillator, wiring in the area enclosed with the broken line in the above figures should be carried out as follows to avoid an adverse effect from wiring capacitance. ? wiring should be as short as possible. ? wiring should not cross other signal lines. ? wiring should not be placed close to a varying high current. ? the potential of the oscillator capacitor ground should be the same as v ss . ? do not ground wiring to a ground pattern in which a high current flows. ? do not fetch a signal from the oscillator. 2. when the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program. min. 1.0 1.0 1.0 85 test conditions v dd = oscillation voltage range after v dd reaches oscil- lation voltage range min. v dd = 4.5 to 6.0 v x1 ic x2 c2 c1 x1 ic x2 c2 c1 x1 x2 m pd74hcu04
39 m pd78052(a), 78053(a), 78054(a) subsystem clock oscillation circuit characteristics (t a = e40 to +85 c, v dd = 2.0 to 6.0 v) min. 32 32 5 notes 1. indicates only oscillation circuit characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after v dd reaches oscillation voltage min. resonator crystal resonator external clock parameter oscillation frequency (f xt ) note 1 oscillation stabilization time note 2 xt1 input frequency (f xt ) note 1 xt1 input high-/low-level width (t xth , t xtl ) test conditions typ. 32.768 1.2 max. 35 2 10 100 15 unit khz s khz m s cautions 1. when using the subsystem clock oscillator, wiring in the area enclosed with the broken line in the above figure should be carried out as follows to avoid an adverse effect from wiring capacitance. ? wiring should be as short as possible. ? wiring should not cross other signal lines. ? wiring should not be placed close to a varying high current. ? the potential of the oscillator capacitor ground should be the same as v ss . ? do not ground wiring to a ground pattern in which a high current flows. ? do not fetch a signal from the oscillator. 2. the subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consumption current, and is more prone to malfunction due to noise than the main system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. v dd = 4.5 to 6.0 v recommended circuit xt2 xt1 ic r1 c4 c3 xt1 xt2
40 m pd78052(a), 78053(a), 78054(a) input c in f = 1 mhz 15 pf capacitance unmeasured pins returned to 0 v. input/output c io f = 1 mhz p01 to p06, p10 to p17, 15 pf capacitance unmeasured pins returned p20 to p27, p30 to p37, to 0 v. p40 to p47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131 p60 to p63 20 pf remark the characteristics of dual-function pins and port pins are the same unless otherwise specified. capacitance (t a = 25 c , v dd = v ss = 0 v) parameter symbol test conditions min. typ. max. unit c3 (pf) c4 (pf) r2 (k w ) min. (v) max. (v) dt-38 32.768 27 20 330 2.0 6.0 (1ta252e00) c1 (pf) c2 (pf) r1 (k w ) min. (v) max. (v) csa5.00mg 5.00 30 30 0 2.0 6.0 cst5.00mgw 5.00 on-chip on-chip 0 2.0 6.0 capacitor on-chip kbr-5.0msa 5.00 33 33 0 2.0 6.0 lead type kbr-5.0mks 5.00 on-chip on-chip 0 2.0 6.0 capacitor on-chip, lead type kbr-5.0mws 5.00 on-chip on-chip 0 2.0 6.0 capacitor on-chip, chip type pbrc 5.00a 5.00 33 33 0 2.0 6.0 chip type tdk corp. ccr4.0mc3 4.00 on-chip on-chip 0 2.0 6.0 capacitor on-chip ccr5.0mc3 5.00 on-chip on-chip 0 2.0 6.0 capacitor on-chip recommended oscillator constant main system clock: ceramic resonator (t a = C40 to +85 c) oscillation voltage range remarks kyocera corp. murata mfg. co., ltd. main system clock: crystal resonator (t a = C10 to +70 c) c1 (pf) c2 (pf) r1 (k w ) min. (v) max. (v) smd-49 3.579545 27 27 1.5 2.0 6.0 oscillation voltage range product name subsystem clock: crystal resonator (t a = C10 to +70 c) daishinku product name frequency (mhz) manufacturer frequency (mhz) frequency (khz) daishinku manufacturer manufacturer recommended oscillator constant recommended oscillator constant recommended oscillator constant oscillation voltage range product name
41 m pd78052(a), 78053(a), 78054(a) parameter symbol test conditions min. typ. max. unit input voltage v ih1 p10 to p17, p21, p23, p30 to p32, v dd = 2.7 to 6.0 v 0.7v dd v dd v high p35 to p37, p40 to p47, p50 to p57, p64 to p67, p71, p120 to p127, 0.8v dd v dd v p130, p131 v ih2 p00 to p06, p20, p22, p24 to p27, v dd = 2.7 to 6.0 v 0.8v dd v dd v p33, p34, p70, p72, reset 0.85v dd v dd v v ih3 p60 to p63 v dd = 2.7 to 6.0 v 0.7v dd 15 v (n-ch open-drain) 0.8v dd 15 v v ih4 x1, x2 v dd = 2.7 to 6.0 v v dd C0.5 v dd v v dd C0.2 v dd v v ih5 xt1/p07, xt2 4.5 v v dd 6.0 v 0.8v dd v dd v 2.7 v v dd < 4.5 v 0.9v dd v dd v 2.0 v v dd < 2.7 v note 0.9v dd v dd v input voltage v il1 p10 to p17, p21, p23, p30 to p32, v dd = 2.7 to 6.0 v 0 0.3v dd v low p35 to p37, p40 to p47, p50 to p57, p64 to p67, p71, p120 to p127, 0 0.2v dd v p130, p131 v il2 p00 to p06, p20, p22, p24 to p27, v dd = 2.7 to 6.0 v 0 0.2v dd v p33, p34, p70, p72, reset 0 0.15v dd v v il3 p60 to p63 4.5 v v dd 6.0 v 0 0.3v dd v 2.7 v v dd < 4.5 v 0 0.2v dd v 0 0.1v dd v v il4 x1, x2 v dd = 2.7 to 6.0 v 0 0.4 v 0 0.2 v v il5 xt1/p07, xt2 4.5 v v dd 6.0 v 0 0.2v dd v 2.7 v v dd < 4.5 v 0 0.1v dd v 2.0 v v dd < 2.7 v note 0 0.1v dd v output voltage v oh v dd = 4.5 to 6.0 v, i oh = C1 ma v dd C1.0 v high i oh = C100 m av dd C0.5 v output voltage v ol1 p50 to p57, p60 to p63 v dd = 4.5 to 6.0 v, 0.4 2.0 v low i ol = 15 ma p01 to p06, p10 to p17, p20 to p27, v dd = 4.5 to 6.0 v, 0.4 v p30 to p37, p40 to p47, p64 to p67, i ol = 1.6 ma p70 to p72, p120 to p127, p130, p131 v ol2 sb0, sb1, sck0 v dd = 4.5 to 6.0 v, 0.2v dd v open-drain, pulled-up (r = 1 k w ) v ol3 i ol = 400 m a 0.5 v dc characteristics (t a = C40 to +85 c, v dd = 2.0 to 6.0 v) remark the characteristics of dual-function pins and port pins are the same unless otherwise specified. note for use as p07, use an inverter to input the inverted phase of p07 to the xt2 pin.
42 m pd78052(a), 78053(a), 78054(a) notes 1. when the pull-up resistor is not included in p60 to p63 (specified by a mask option), the C200 m a (max.) low-level input leakage current flows only at the 1.5-clock interval (no wait) when the read instruction to the port 6 (p6) and port mode register 6 (pm6) is executed. other than the 1.5-clock interval, C3 m a (max.) current flows. 2. a software pull-up resistor can be used only in the range of v dd = 2.7 to 6.0 v. remark the characteristics of dual-function pins and port pins are the same unless otherwise specified. dc characteristics (t a = C40 to +85 c, v dd = 2.0 to 6.0 v) parameter symbol test conditions min. typ. max. unit input leakage i lih1 v in = v dd p00 to p06, p10 to p17, p20 to p27, 3 m a current high p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p72, p120 to p127, p130, p131, reset i lih2 x1, x2, xt1/p07, xt2 20 m a i lih3 v in = 15 v p60 to p63 80 m a input leakage i lil1 v in = 0 v p00 to p06, p10 to p17, p20 to p27, C3 m a current low p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131, reset i lil2 x1, x2, xt1/p07, xt2 C20 m a i lil3 p60 to p63 C3 note 1 m a output leakage i loh v out = v dd 3 m a current high output leakage i lol v out = 0 v C3 m a current low mask option pull- r 1 v in = 0 v, p60 to p63 20 40 90 k w up resistor software pull- r 2 v in = 0 v, p01 to p06, 4.5 v v dd 6.0 v 15 40 90 k w up resistor note 2 p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57, p64 to p67 , 2.7 v v dd < 4.5 v 20 500 k w p70 to p72, p120 to p127, p130, p131
43 m pd78052(a), 78053(a), 78054(a) v dd = 5.0 v 10 % note 5 412ma v dd = 3.0 v 10 % note 6 0.6 1.8 ma v dd = 2.2 v 10 % note 6 0.35 1.05 ma v dd = 5.0 v 10 % note 5 6.5 19.5 ma v dd = 3.0 v 10 % note 6 0.8 2.4 ma v dd = 5.0 v 10 % 1.4 4.2 ma v dd = 3.0 v 10 % 0.5 1.5 ma v dd = 2.2 v 10 % 280 840 m a v dd = 5.0 v 10 % 1.6 4.8 ma v dd = 3.0 v 10 % 0.65 1.95 ma v dd = 5.0 v 10 % 60 120 m a v dd = 3.0 v 10 % 32 64 m a v dd = 2.2 v 10 % 24 48 m a v dd = 5.0 v 10 % 25 55 m a v dd = 3.0 v 10 % 5 15 m a v dd = 2.2 v 10 % 2.5 12.5 m a v dd = 5.0 v 10 % 1 30 m a v dd = 3.0 v 10 % 0.5 10 m a v dd = 2.2 v 10 % 0.3 10 m a v dd = 5.0 v 10 % 0.1 30 m a v dd = 3.0 v 10 % 0.05 10 m a v dd = 2.2 v 10 % 0.05 10 m a parameter symbol test conditions min. typ. max. unit notes 1. the current flowing in the v dd pin. not including the current flowing in the a/d converter, d/a converter, and on-chip pull-up resistor. 2. f xx =f x /2 operation (when the oscillation mode selection register (osms) is set to 00h) 3. f xx = f x operation (when the osms is set to 01h) 4. when the main system clock is stopped 5. high-speed mode operation (when the processor clock control register (pcc) is set to 00h) 6. low-speed mode operation (when the pcc is set to 04h) remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency dc characteristics (t a = C40 to +85 c, v dd = 2.0 to 6.0 v) i dd1 5.0-mhz crystal oscillation operating mode (f xx = 2.5 mhz) note 2 5.0-mhz crystal oscillation operating mode (f xx = 5.0 mhz) note 3 5.0-mhz crystal oscillation halt mode (f xx = 5.0 mhz) note 3 i dd2 5.0-mhz crystal oscillation halt mode (f xx = 2.5 mhz) note 2 i dd3 32.768-khz crystal oscillation operating mode note 4 i dd4 32.768-khz crystal oscillation halt mode note 4 i dd6 xt1 = v dd stop mode when feedback resistor is unused power supply current note 1 i dd5 xt1 = v dd stop mode when feedback resistor is used
44 m pd78052(a), 78053(a), 78054(a) ac characteristics (1) basic operation (t a = e40 to +85 c, v dd = 2.0 to 6.0 v) parameter symbol test conditions min. typ. max. unit cycle time t cy operating on main v dd = 2.7 to 6.0 v 0.8 64 m s (min. instruction system clock 2.2 64 m s execution time) 4.5 v v dd 6.0 v 0.4 32 m s 2.7 v v dd < 4.5 v 0.8 32 m s operating on subsystem clock 40 122 125 m s ti00, ti01, ti1, ti2 f ti v dd = 4.5 to 6.0 v 0 4 mhz input frequency 0 275 khz ti00 input t tih , 8/f sam note 3 m s high-/low-level width t til ti01, ti1, ti2 input t tih ,v dd = 4.5 to 6.0 v 100 ns high-/low-level width t til 1.8 m s interrupt input t inth , intp0 8/f sam note 3 m s high-/low-level t intl intp1 to intp6, kr0 to kr7 v dd = 2.7 to 6.0 v 10 m s width 20 m s reset t rsl v dd = 2.7 to 6.0 v 10 m s low-level width 20 m s f xx = f x /2 note 1 f xx = f x note 2 remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency notes 1. when oscillation mode selection register (osms) is set to 00h 2. when osms is set to 01h 3. in combination with bits 0 (scs0) and 1 (scs1) of sampling clock selection register, f sam is selectable between f xx /2 n , f xx /32, f xx /64, and f xx /128 (when n = 0 to 4).
45 m pd78052(a), 78053(a), 78054(a) t cy vs v dd (at f xx = f x main system clock operation) t cy vs v dd (at f xx = f x /2 main system clock operation) 60 10 2.0 1.0 0.5 0.4 0 1234 56 supply voltage v dd [v] operation guaranteed range 60 10 2.0 1.0 0.5 0.4 0 1234 56 supply voltage v dd [v] operation guaranteed range cycle time t cy [ s] m cycle time t cy [ s] m
46 m pd78052(a), 78053(a), 78054(a) remarks 1. mcs: oscillation mode selection register (osms) bit 0 2. pcc2 to pcc0: processor clock control register (pcc) bit 2 to bit 0 3. t cy = t cy /4 4. n indicates the number of waits. parameter symbol test conditions min. max. unit astb high-level width t asth 0.85t cy C50 ns address setup time t ads 0.85t cy C50 ns address hold time t adh 50 ns data input time from address t add1 (2.85+2n)t cy C80 ns t add2 (4+2n)t cy C100 ns data input time from rd t rdd1 (2+2n)t cy C100 ns t rdd2 (2.85+2n)t cy C100 ns read data hold time t rdh 0ns rd low-level width t rdl1 (2+2n)t cy C60 ns t rdl2 (2.85+2n)t cy C60 ns wait input time from rd t rdwt1 0.85t cy C50 ns t rdwt2 2t cy C60 ns wait input time from wr t wrwt 2t cy C60 ns wait low-level width t wtl (1.15+2n)t cy (2+2n)t cy ns write data setup time t wds (2.85+2n)t cy C100 ns write data hold time t wdh 20 ns wr low-level width t wrl (2.85+2n)t cy C60 ns rd delay time from astb t astrd 25 ns wr delay time from astb t astwr 0.85t cy +20 ns astb - delay time from t rdast 0.85t cy C10 1.15t cy +20 ns rd - in external fetch address hold time from t rdadh 0.85t cy C50 1.15t cy +50 ns rd - in external fetch write data output time from rd - t rdwd 40 ns write data output time from wr t wrwd 050ns address hold time from wr - t wradh 0.85t cy 1.15t cy +40 ns rd - delay time from wait - t wtrd 1.15t cy +40 3.15t cy +40 ns wr - delay time from wait - t wtwr 1.15t cy +30 3.15t cy +30 ns (2) read/write operation (a) when mcs = 1, pcc2 to pcc0 = 000b (t a = C40 to +85 c, v dd = 4.5 to 6.0 v)
47 m pd78052(a), 78053(a), 78054(a) (b) except when mcs = 1, pcc2 to pcc0 = 000b (t a = e40 to +85 c, v dd = 2.0 to 6.0 v) (1/2) parameter symbol test conditions min. max. unit astb high-level width t asth v dd = 2.7 to 6.0 v t cy C80 ns t cy C150 ns address setup time t ads v dd = 2.7 to 6.0 v t cy C80 ns t cy C150 ns address hold time t adh v dd = 2.7 to 6.0 v 0.4t cy C10 ns 0.37t cy C40 ns data input time from address t add1 v dd = 2.7 to 6.0 v (3+2n)t cy C160 ns (3+2n)t cy C320 ns t add2 v dd = 2.7 to 6.0 v (4+2n)t cy C200 ns (4+2n)t cy C300 ns data input time from rd t rdd1 v dd = 2.7 to 6.0 v (1.4+2n)t cy C70 ns (1.37+2n)t cy C120 ns t rdd2 v dd = 2.7 to 6.0 v (2.4+2n)t cy C70 ns (2.37+2n)t cy C120 ns read data hold time t rdh 0ns rd low-level width t rdl1 v dd = 2.7 to 6.0 v (1.4+2n)t cy C20 ns (1.37+2n)t cy C20 ns t rdl2 v dd = 2.7 to 6.0 v (2.4+2n)t cy C20 ns (2.37+2n)t cy C20 ns wait input time from rd t rdwt1 v dd = 2.7 to 6.0 v t cy C100 ns t cy C200 ns t rdwt2 v dd = 2.7 to 6.0 v 2t cy C100 ns 2t cy C200 ns wait input time from wr t wrwt v dd = 2.7 to 6.0 v 2t cy C100 ns 2t cy C200 ns wait low-level width t wtl (1+2n)t cy (2+2n)t cy ns write data setup time t wds v dd = 2.7 to 6.0 v (2.4+2n)t cy C60 ns (2.37+2n)t cy C100 ns write data hold time t wdh 20 ns wr low-level width t wrl v dd = 2.7 to 6.0 v (2.4+2n)t cy C20 ns (2.37+2n)t cy C20 ns rd delay time from astb t astrd v dd = 2.7 to 6.0 v 0.4t cy C30 ns 0.37t cy C50 ns wr delay time from astb t astwr v dd = 2.7 to 6.0 v 1.4t cy C30 ns 1.37t cy C50 ns remarks 1. mcs: oscillation mode selection register (osms) bit 0 2. pcc2 to pcc0: processor clock control register (pcc) bit 2 to bit 0 3. t cy = t cy /4 4. n indicates the number of waits.
48 m pd78052(a), 78053(a), 78054(a) (b) except when mcs = 1, pcc2 to pcc0 = 000b (t a = e40 to +85 c, v dd = 2.0 to 6.0 v) (2/2) parameter symbol test conditions min. max. unit astb - delay time from t rdast t cy C10 t cy +20 ns rd - in external fetch address hold time from t rdadh t cy C50 t cy +50 ns rd - in external fetch write data output time from rd - t rdwd v dd = 2.7 to 6.0 v 0.4t cy C20 ns 0.37t cy C40 ns write data output time from wr t wrwd v dd = 2.7 to 6.0 v 0 60 ns 0 120 ns address hold time from wr - t wradh v dd = 2.7 to 6.0 v t cy t cy +60 ns t cy t cy +120 ns rd - delay time from wait - t wtrd v dd = 2.7 to 6.0 v 0.6t cy +180 2.6t cy +180 ns 0.63t cy +350 2.63t cy +350 ns wr - delay time from wait - t wtwr v dd = 2.7 to 6.0 v 0.6t cy +120 2.6t cy +120 ns 0.63t cy +240 2.63t cy +240 ns remarks 1. mcs: oscillation mode selection register (osms) bit 0 2. pcc2 to pcc0: processor clock control register (pcc) bit 2 to bit 0 3. t cy = t cy /4 4. n indicates the number of waits.
49 m pd78052(a), 78053(a), 78054(a) parameter symbol test conditions min. typ. max. unit 4.5 v v dd 6.0 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 3200 ns t kh1 , t kl1 v dd = 4.5 to 6.0 v t kcy1 /2C50 ns t kcy1 /2C100 ns t sik1 4.5 v v dd 6.0 v 100 ns 2.7 v v dd < 4.5 v 150 ns 300 ns t ksi1 400 ns 300 ns sck0 cycle time sck0 high-/low-level width (3) serial interface (t a = C40 to +85 c, v dd = 2.0 to 6.0 v) (a) serial interface channel 0 (i) 3-wire serial i/o mode (sck0... internal clock output) c = 100 pf note note c is the load capacitance of so0 output line. parameter symbol test conditions min. typ. max. unit 4.5 v v dd 6.0 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 3200 ns t kh2 , t kl2 4.5 v v dd 6.0 v 400 ns 2.7 v v dd < 4.5 v 800 ns 1600 ns t sik2 100 ns t ksi2 400 ns 300 ns sck0 rise, fall time t r2 , t f2 when using external device 160 ns expansion function when not using external 1000 ns device expansion function sck0 cycle time sck0 high-/low-level width so0 output delay time from sck0 c = 100 pf note si0 hold time (from sck0 - ) si0 setup time (to sck0 - ) t kso2 t kcy1 t kcy2 note c is the load capacitance of so0 output line. (ii) 3-wire serial i/o mode (sck0... external clock input) si0 hold time (from sck0 - ) so0 output delay time from sck0 t kso1 si0 setup time (to sck0 - )
50 m pd78052(a), 78053(a), 78054(a) parameter symbol test conditions min. typ. max. unit v dd = 4.5 to 6.0 v 800 ns 3200 ns v dd = 4.5 to 6.0 v t kcy3 /2C50 ns t kcy3 /2C150 ns v dd = 4.5 to 6.0 v 100 ns 300 ns r = 1 k w , v dd = 4.5 to 6.0 v 0 250 ns c = 100 pf note 0 1000 ns t kcy3 ns t kcy3 ns t kcy3 ns sb0, sb1 output delay time from sck0 sb0, sb1 hold time (from sck0 -) (iii) sbi mode (sck0... internal clock output) t kcy3 t kh3 , t kl3 t ksi3 t sik3 t kso3 t ksb t sbk t sbl sb0, sb1 setup time (to sck0 - ) t sbh t kcy3 /2 ns t kcy3 ns sck0 cycle time sck0 high-/low-level width sb0, sb1 from sck0 - sck0 from sb0, sb1 sb0, sb1 high-level width sb0, sb1 low-level width note r and c are the load resistance and load capacitance of the sck0 and sb0, sb1 output lines.
51 m pd78052(a), 78053(a), 78054(a) (iv) sbi mode (sck0... external clock input) parameter symbol test conditions min. typ. max. unit v dd = 4.5 to 6.0 v 800 ns 3200 ns v dd = 4.5 to 6.0 v 400 ns 1600 ns v dd = 4.5 to 6.0 v 100 ns 300 ns r = 1 k w , v dd = 4.5 to 6.0 v 0 300 ns c = 100 pf note 0 1000 ns t kcy4 ns t kcy4 ns t kcy4 ns sck0 cycle time t kcy4 t kh4 , t kl4 t ksi4 t sik4 t kso4 t ksb sb0, sb1 setup time (to sck0 - ) sck0 high-/low-level width sb0, sb1 hold time (from sck0 - ) sb0, sb1 output delay time from sck0 sb0, sb1 from sck0 - sck0 from sb0, sb1 sb0, sb1 high-level width sb0, sb1 low-level width t kcy4 /2 ns t kcy4 ns sck0 rise, fall time t r4 , t f4 when using external device 160 ns expansion function when not using external 1000 ns device expansion function t sbk t sbh t sbl note r and c are the load resistance and load capacitance of the sb0, sb1 output line.
52 m pd78052(a), 78053(a), 78054(a) parameter symbol test conditions min. typ. max. unit t kcy6 v dd = 2.7 to 6.0 v 1600 ns 3200 ns t kh6 v dd = 2.7 to 6.0 v 650 ns 1300 ns t kl6 v dd = 2.7 to 6.0 v 800 ns 1600 ns t sik6 100 ns t ksi6 t kcy6 /2 ns t kso6 v dd = 4.5 to 6.0 v 0 300 ns 0 500 ns sck0 rise, fall time t r6 , t f6 when using external device 160 ns expansion function when not using external 1000 ns device expansion function parameter symbol test conditions min. typ. max. unit t kcy5 r = 1 k w , v dd = 2.7 to 6.0 v 1600 ns c = 100 pf note 3200 ns t kh5 v dd = 2.7 to 6.0 v t kcy5 /2C160 ns t kcy5 /2C190 ns t kl5 v dd = 4.5 to 6.0 v t kcy5 /2C50 ns t kcy5 /2C100 ns t sik5 4.5 v v dd 6.0 v 300 ns 2.7 v v dd < 4.5 v 350 ns 400 ns t ksi5 600 ns t kso5 0 300 ns (vi) 2-wire serial i/o mode (sck0... external clock input) sck0 low-level width sb0, sb1 setup time (to sck0 - ) sb0, sb1 hold time (from sck0 - ) sb0, sb1 output delay time from sck0 r = 1 k w , c = 100 pf note (v) 2-wire serial i/o mode (sck0... internal clock output) sck0 cycle time sck0 high-level width sck0 low-level width sb0, sb1 setup time (to sck0 - ) sb0, sb1 hold time (from sck0 - ) sb0, sb1 output delay time from sck0 note r and c are the load resistance and load capacitance of the sck0 and sb0, sb1 output lines. note r and c are the load resistance and load capacitance of the sb0, sb1 output line. sck0 cycle time sck0 high-level width
53 m pd78052(a), 78053(a), 78054(a) parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy7 4.5 v v dd 6.0 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 3200 ns sck1 high-/low-level t kh7 , v dd = 4.5 to 6.0 v t kcy7 /2C50 ns width t kl7 t kcy7 /2C100 ns si1 setup time t sik7 4.5 v v dd 6.0 v 100 ns (to sck1 - ) 2.7 v v dd < 4.5 v 150 ns 300 ns si1 hold time t ksi7 400 ns (from sck1 - ) so1 output delay time t kso7 c = 100 pf note 300 ns from sck1 (b) serial interface channel 1 (i) 3-wire serial i/o mode (sck1... internal clock output) note c is the load capacitance of the so1 output line. (ii) 3-wire serial i/o mode (sck1... external clock input) parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy8 4.5 v v dd 6.0 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 3200 ns sck1 high-/low-level t kh8 , 4.5 v v dd 6.0 v 400 ns width t kl8 2.7 v v dd < 4.5 v 800 ns 1600 ns si1 setup time t sik8 100 ns (to sck1 - ) si1 hold time t ksi8 400 ns (from sck1 - ) so1 output delay t kso8 c = 100 pf note 300 ns time from sck1 sck1 rise, fall time t r8 , t f8 when using external device 160 ns expansion function when not using external 1000 ns device expansion function note c is the load capacitance of the so1 output line.
54 m pd78052(a), 78053(a), 78054(a) parameter symbol test conditions min. typ. max. unit 4.5 v v dd 6.0 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 3200 ns v dd = 4.5 to 6.0 v t kcy9 /2C50 ns t kcy9 /2C100 ns 4.5 v v dd 6.0 v 100 ns 2.7 v v dd < 4.5 v 150 ns 300 ns 400 ns c = 100 pf note 300 ns t kcy9 /2C100 t kcy9 /2+100 ns v dd = 2.7 to 6.0 v t kcy9 C30 t kcy9 +30 ns t kcy9 C60 t kcy9 +60 ns 100 ns 4.5 v v dd 6.0 v 100 ns 2.7 v v dd < 4.5 v 150 ns 200 ns 2t kcy9 ns parameter symbol test conditions min. typ. max. unit 4.5 v v dd 6.0 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 3200 ns 4.5 v v dd 6.0 v 400 ns 2.7 v v dd < 4.5 v 800 ns 1600 ns 100 ns 400 ns c = 100 pf note 300 ns sck1 rise, fall time t r10 , t f10 when using external device 160 ns expansion function when not using external 1000 ns device expansion function sck1 cycle time sck1 high-/low-level width si1 setup time (to sck1 - ) si1 hold time (from sck1 - ) so1 output delay time from sck1 t kcy9 t kh9 , t kl9 note c is the load capacitance of the so1 output line. sck1 cycle time sck1 high-/low-level width si1 setup time (to sck1 - ) si1 hold time (from sck1 - ) so1 output delay time from sck1 stb - from sck1 - strobe signal high-level width busy signal setup time (to busy signal detection timing) busy signal hold time (from busy signal detection timing) sck1 from busy inactive t sik9 t ksi9 t kso9 t sbd t bys t byh t sps note c is the load capacitance of the so1 output line. t kcy10 t kh10 , t kl10 t sik10 t ksi10 t kso10 (iii) 3-wire serial i/o mode with automatic transmit/receive function (sck1...internal clock output) (iv) 3-wire serial i/o mode with automatic transmit/receive function (sck1...external clock input) t sbw
55 m pd78052(a), 78053(a), 78054(a) parameter symbol test conditions min. typ. max. unit sck2 cycle time t kcy12 4.5 v v dd 6.0 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 3200 ns sck2 high-/low-level t kh12 , 4.5 v v dd 6.0 v 400 ns width t kl12 2.7 v v dd < 4.5 v 800 ns 1600 ns si2 setup time t sik12 100 ns (to sck2 - ) si2 hold time t ksi12 400 ns (from sck2 - ) so2 output delay t kso12 c = 100 pf note 300 ns time from sck2 sck2 rise, fall time t r12 , t f12 when using external 160 ns device expansion function when not using external 1000 ns device expansion function parameter symbol test conditions min. typ. max. unit sck2 cycle time t kcy11 4.5 v v dd 6.0 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 3200 ns sck2 high-/low-level t kh11 , v dd = 4.5 to 6.0 v t kcy11 /2C50 ns width t kl11 t kcy11 /2C100 ns si2 setup time t sik11 4.5 v v dd 6.0 v 100 ns (to sck2 - ) 2.7 v v dd < 4.5 v 150 ns 300 ns si2 hold time t ksi11 400 ns (from sck2 - ) so2 output delay time t kso11 c = 100 pf note 300 ns from sck2 (c) serial interface channel 2 (i) 3-wire serial i/o mode (sck2... internal clock output) note c is the load capacitance of the so2 output line. (ii) 3-wire serial i/o mode (sck2... external clock input) note c is the load capacitance of the so2 output line.
56 m pd78052(a), 78053(a), 78054(a) parameter symbol min. typ. max. unit t kcy13 4.5 v v dd 6.0 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 3200 ns t kh13 , 4.5 v v dd 6.0 v 400 ns t kl13 2.7 v v dd < 4.5 v 800 ns 1600 ns 4.5 v v dd 6.0 v 39063 bps 2.7 v v dd < 4.5 v 19531 bps 9766 bps asck rise, fall time t r13 , v dd = 4.5 to 6.0 v, 1000 ns t f13 when not using external device expansion function 160 ns parameter symbol min. typ. max. unit 4.5 v v dd 6.0 v 78125 bps 2.7 v v dd < 4.5 v 39063 bps 19531 bps (iii) uart mode (dedicated baud rate generator output) transfer rate (iv) uart mode (external clock input) asck cycle time asck high-/low-level width transfer rate test conditions test conditions
57 m pd78052(a), 78053(a), 78054(a) ac timing test point (excluding x1, xt1 input) ti timing clock timing 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points t xl t xh 1/f x v il4 (max.) t xtl t xth 1/f xt v il5 (max.) x1 input xt1 input v ih5 (min.) v ih4 (min.) 1/f ti t tih t til ti00, ti01, ti1, ti2
58 m pd78052(a), 78053(a), 78054(a) read/write operation external fetch (no wait) : external fetch (wait insertion) : t asth t adh t add1 hi-z t ads t rdadh t rdast t astrd t rdl1 t rdh a8 to a15 ad0 to ad7 astb rd t wtrd t wtl t rdwt1 wait t rdd1 upper 8-bit address operation code lower 8-bit address t asth t adh t add1 hi-z t ads t rdd1 t rdadh t rdast t astrd t rdl1 t rdh a8 to a15 ad0 to ad7 astb rd upper 8-bit address operation code lower 8-bit address
59 m pd78052(a), 78053(a), 78054(a) external data access (no wait) : external data access (wait insertion) : t astrd t asth t adh t add2 hi-z t ads t rdl2 a8 to a15 ad0 to ad7 astb rd t wds t wrl wr t rdh hi-z hi-z t wrwd t astwr t wradh upper 8-bit address write data read data lower 8-bit address t rdd2 t wdh t rdwd t astrd t asth t adh t add2 hi-z t ads t rdl2 a8 to a15 ad0 to ad7 astb rd t wds t wrl wr t rdh hi-z hi-z t wrwd t astwr t wradh upper 8-bit address write data read data lower 8-bit address t rdd2 t wdh t rdwt2 t wtl t wrwt t wtwr t wtl wait t wtrd t rdwd
60 m pd78052(a), 78053(a), 78054(a) serial transfer timing 3-wire serial i/o mode : t kcym t klm t khm sck0 to sck2 si0 to si2 so0 to so2 t sikm t ksim t ksom input data output data t rn t fn m = 1, 2, 7, 8, 11, 12 n = 2, 8, 12 t sik3,4 t kcy3,4 t kl3,4 t kh3,4 sck0 t sbl t sbh t ksb t sbk t ksi3, 4 t kso3,4 sb0, sb1 t r4 t f4 t sik3,4 t kcy3,4 t kl3,4 t kh3,4 sck0 t ksb t sbk t ksi3,4 t kso3,4 sb0, sb1 t r4 t f4 sbi mode (command signal transfer) : sbi mode (bus release signal transfer) :
61 m pd78052(a), 78053(a), 78054(a) 2-wire serial i/o mode : 3-wire serial i/o mode with automatic transmit/receive function (busy processing) : note the signal is not actually driven low here; it is shown as such to indicate the timing. 3-wire serial i/o mode with automatic transmit/receive function : t kso5,6 t sik5,6 t kcy5,6 t kl5,6 t kh5,6 sck0 t ksi5,6 sb0, sb1 t f6 t r6 t sbw t sbd t kcy9,10 t kh9,10 t ksi9,10 t kso9,10 t sik9,10 d2 d1 d0 d7 d7 d2 d1 d0 so1 si1 sck1 stb t r10 t kl9,10 t f10 t bys sck1 t sps busy (active high) 789 note 10 note 10+n note 1 t byh
62 m pd78052(a), 78053(a), 78054(a) parameter symbol test conditions min. typ. max. unit 8 8 8 bit 2.7 v av ref0 av dd 0.6 % 2.0 v av ref0 < 2.7 v 1.4 % t conv 19.1 200 m s t samp 12/fxx m s v ian av ss av ref0 v av ref0 2.0 av dd v r airef0 4 14 k w uart mode (external clock input) : t kcy13 t kh13 t kl13 t f13 t r13 asck resolution overall error settling time output resistance analog reference voltage av ref1 current d/a converter characteristics (t a = C40 to +85 c, v dd = 2.0 to 6.0 v, av ss = v ss = 0 v) note overall error excluding quantization error ( 1/2 lsb). it is indicated as a ratio to the full-scale value. remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency a/d converter characteristics (t a = C40 to +85 c, av dd = v dd = 2.0 to 6.0 v, av ss = v ss = 0 v) resolution overall error note conversion time sampling time analog input voltage reference voltage resistance between av ref0 and av ss notes 1. r and c denote d/a converter output pin load resistance and load capacitance, respectively. 2. value for one d/a converter channel remark dacs0, dacs1: d/a conversion value setting register 0, 1 parameter symbol test conditions min. typ. max. unit 8 bit r = 2 m w note 1 1.2 % r = 4 m w note 1 0.8 % r = 10 m w note 1 0.6 % c = 30 pf 4.5 v av ref1 6.0 v 10 m s note 1 2.7 v av ref1 < 4.5 v 15 m s 2.0 v av ref1 < 2.7 v 20 m s r o dacs0, dacs1 = 55h note 2 10 k w av ref1 2.0 v dd v i ref1 note 2 1.5 ma
63 m pd78052(a), 78053(a), 78054(a) parameter symbol test conditions min. typ. max. unit data retention power v dddr 1.8 6.0 v supply voltage data retention i dddr v dddr = 1.8 v 0.1 10 m a power supply subsystem clock stop and current feedback resistor disconnected release signal set time t srel 0 m s oscillation stabiliza- t wait release by reset 2 17 /fx ms tion wait time release by interrupt note ms data memory stop mode low supply voltage data retention characteristics (t a = C40 to +85 c) note in combination with bits 0 to 2 (osts0 to osts2) of oscillation stabilization time select register (osts), selection of 2 12 /f xx and 2 14 /f xx to 2 17 /f xx is possible. remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt signal) t srel t wait v dd stop instruction execution stop mode data retention mode halt mode operating mode standby release signal (interrupt request) v dddr t srel t wait v dd reset stop instruction execution stop mode data retention mode internal reset operation halt mode operating mode v dddr
64 m pd78052(a), 78053(a), 78054(a) interrupt input timing reset input timing t intl t inth intp0 to intp6 t rsl reset
65 m pd78052(a), 78053(a), 78054(a) 12. characteristic curves (for reference only) i dd vs v dd (fx = fxx = 5.0 mhz) (t a = 25 ?c) pcc = 01h pcc = 00h pcc = 02h pcc = 03h pcc = 04h pcc = 30h halt (x1 oscillation, xt1 oscillation) pcc = b0h halt (x1 stop, xt1 oscillation) 0 23456789 0.001 0.005 0.01 0.05 0.1 1.0 5.0 10.0 supply voltage v dd (v) supply current i dd (ma) 0.5
66 m pd78052(a), 78053(a), 78054(a) i dd vs v dd (fx = 5.0 mhz, fxx = 2.5 mhz) (t a = 25 ?c) pcc = 00h pcc = 01h pcc = 02h pcc = 03h pcc = 30h halt (x1 oscillation, xt1 oscillation) pcc = b0h halt (x1 stop, xt1 oscillation) 0 23456789 0.001 0.005 0.01 0.05 0.1 1.0 5.0 10.0 supply voltage v dd (v) supply current i dd (ma) pcc = 04h 0.5
67 m pd78052(a), 78053(a), 78054(a) 13. package drawing remark dimensions and materials of es product are the same as those of mass-production products. 80 pin plastic qfp (14 14) item millimeters inches note each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. l 0.8 0.2 0.031 +0.009 ?.008 m 0.15 0.006 n 0.10 0.004 p 2.7 0.106 a 17.2 0.4 0.677 0.016 b 14.0 0.2 0.551 +0.009 ?.008 c 14.0 0.2 0.551 +0.009 ?.008 d 17.2 0.4 0.677 0.016 f 0.825 0.032 g 0.825 0.032 h 0.30 0.10 0.012 +0.004 ?.005 i 0.13 0.005 j 0.65 (t.p.) 0.026 (t.p.) q 0.1 0.1 0.004 0.004 r5 5 5 5 +0.10 ?.05 +0.004 ?.003 m m l k j h q p n r detail of lead end i g k 1.6 0.2 0.063 0.008 60 61 40 80 1 21 20 41 a b cd f s s80gc-65-3b9-4 s 3.0 max. 0.119 max.
68 m pd78052(a), 78053(a), 78054(a) 14. recommended soldering conditions this product should be soldered and mounted under the conditions recommended in the table below. for detail of recommended soldering conditions, refer to the information document semiconductor device mounting technology manual (c10535e). for soldering methods and conditions other than those recommended below, contact our sales representative. table 14-1. surface mounting type soldering conditions m pd78052gc(a)- -3b9 : 80-pin plastic qfp (14 14 mm) m pd78053gc(a)- -3b9 : 80-pin plastic qfp (14 14 mm) m pd78054gc(a)- -3b9 : 80-pin plastic qfp (14 14 mm) ir35-00-3 package peak temperature: 235 c, reflow time: 30 seconds or below (at 210 c or higher), number of reflow processes: 3 max. package peak temperature: 215 c, reflow time: 40 seconds or below (at 200 c or higher), number of reflow processes: 3 max. solder temperature: 260 c or below, flow time: 10 seconds or below, number of flow processes: once, preheating temperature: 120 c or below (package surface temperature) pin temperature: 300 c or below, time: 3 seconds or below (per device side) soldering conditions soldering method infrared reflow symbol vps wave soldering pin partial heating vp15-00-3 ws60-00-1 caution use of more than one soldering method should be avoided (except for the pin partial heating method).
69 m pd78052(a), 78053(a), 78054(a) ie-78000-r in-circuit emulator common to 78k/0 series ie-78000-r-a in-circuit emulator common to 78k/0 series (for integrated debugger) ie-78000-r-bk break board common to 78k/0 series ie-78064-r-em emulation board common to m pd78064 subseries ep-78230gc-r emulation probe common to m pd78234 subseries ev-9200gc-80 socket to be mounted on the target system board manufactured for 80-pin plastic qfp sm78k0 note 5, 6, 7 system simulator common to 78k/0 series id78k0 note 4, 5, 6, 7 integrated debugger for ie-78000-r-a sd78k/0 note 1, 2 screen debugger for ie-78000-r df78054 note 1, 2, 4, 5, 6, 7 device file for m pd78054 subseries appendix a. development tools the following development tools are available for system development using the m pd78054 subseries. language processing software ra78k/0 note 1, 2, 3, 4 cc78k/0 note 1, 2, 3, 4 df78054 note 1, 2, 3, 4 cc78k/0-l note 1, 2, 3, 4 assembler package common to 78k/0 series c compiler package common to 78k/0 series device file common to m pd78054 subseries c compiler library source file common to 78k/0 series debugging tools notes 1. pc-9800 series (ms-dos tm ) based 2. ibm pc/at tm and its compatibles (pc dos tm /ibm dos tm /ms-dos) based 3. hp9000 series 300 tm (hp-ux tm ) based 4. hp9000 series 700 tm (hp-ux) based, sparcstation tm (sunos tm ) based, ews4800 series (ews-ux/ v) based 5. pc-9800 series (ms-dos + windows tm ) based 6. ibm pc/at and its compatibles (pc dos/ibm dos/ms-dos + windows) based 7. news tm (news-os tm ) based remarks 1. for third party development tools, see the 78k/0 series selection guide (u11126e) . 2. ra78k/0, cc78k/0, sm78k0, id78k0, and sd78k/0 are used in combination with df78054.
70 m pd78052(a), 78053(a), 78054(a) rx78k/0 note 1, 2, 3, 4 real-time os for 78k/0 series mx78k0 note 1, 2, 3, 4 os for 78k/0 series real-time os notes 1. pc-9800 series (ms-dos) based 2. ibm pc/at and its compatibles (pc dos/ibm dos/ms-dos) based 3. hp9000 series 300 (hp-ux ) based 4. hp9000 series 700 (hp-ux) based, sparcstation (sunos) based, ews4800 series (ews-ux/v) based 5. ibm pc/at and its compatibles (pc dos/ibm dos/ms-dos + windows) based fuzzy inference development support system fuzzy knowledge data input tool translator fuzzy inference module fuzzy inference debugger fe9000 note 1 /fe9200 note 5 ft9080 note 1 /ft9085 note 2 fi78k0 note 1, 2 fd78k0 note 1, 2 remarks 1. for third party development tools, see the 78k/0 series selection guide (u11126e) . 2. rx78k/0 is used in combination with df78054.
71 m pd78052(a), 78053(a), 78054(a) document name document no. document no. (english) (japanese) ra78k series assembler package operation eeu-1399 eeu-809 language eeu-1404 eeu-815 ra78k series structured assembler preprocessor eeu-1402 eeu-817 ra78k0 assembler package operation u11802e u11802j assembly language u11801e u11801j structured assembly language u11789e u11789j cc78k series c compiler operation eeu-1280 eeu-656 language eeu-1284 eeu-655 cc78k/0 c compiler operation u11517e u11517j language u11518e u11518j cc78k/0 c compiler application note programming know-how eea-1208 eea-618 cc78k series library source file C eeu-777 ie-78000-r u11376e eeu-810 ie-78000-r-a u10057e u10057j ie-78000-r-bk eeu-1427 eeu-867 ie-78064-r-em eeu-1443 eeu-905 ep-78230 eeu-1515 eeu-985 appendix b. related documents device related documents development tool related documents (users manual) document name document no. document no. (english) (japanese) m pd78054, 78054y subseries users manual u11747e u11747j m pd78052(a), 78053(a), 78054(a) data sheet this document u12171j 78k/0 series users manual instructions ieu-1372 ieu-849 78k/0 series instruction set C u10904j 78k/0 series instruction table C u10903j m pd78054 subseries special function register table C u10102j 78k/0 series application note fundamental (iii) u10182e iea-767 floating-point arithmetic programs iea-1289 iea-718 caution the above related documents are subject to change without notice. for design purpose, etc., be sure to use the latest documents.
72 m pd78052(a), 78053(a), 78054(a) document name document no. document no. (english) (japanese) 78k/0 series real-time os basics C u11537j installation C u11536j technical C u11538j 78k/0 series os mx78k0 basics C eeu-5010 fuzzy knowledge data input tools eeu-1438 eeu-829 78k/0, 78k/ii, 87ad series eeu-1444 eeu-862 fuzzy inference development support system translator 78k/0 series fuzzy inference development support system eeu-1441 eeu-858 fuzzy inference module 78k/0 series fuzzy inference development support system eeu-1458 eeu-921 fuzzy inference knowledge debugger embedded software documents (users manual) document name document no. document no. (english) (japanese) ic package manual c10943x semiconductor device mounting technology manual c10535e c10535j quality grades on nec semiconductor devices c11531e c11531j nec semiconductor device reliability/quality control system c10983e c10983j electrostatic discharge (esd) test C mem-539 guide to quality assurance for semiconductor devices mei-1202 c11893j microcomputer product series guide C u11416j other documents caution the above related documents are subject to change without notice. for design purpose, etc., be sure to use the latest documents. document name document no. document no. (english) (japanese) sm78k0 system simulator, windows based reference u10181e u10181j sm78k series system simulator external part user open u10092e u10092j interface specifications id78k0 integrated debugger, ews based reference C u11151j id78k0 integrated debugger, pc based reference u11539e u11539j id78k0 integrated debugger, windows based guide u11649e u11649j sd78k/0 screen debugger introduction C eeu-852 pc-9800 series (ms-dos) based reference C u10952j sd78k/0 screen debugger introduction eeu-1414 eeu-5024 ibm pc/at (pc dos) based reference u11279e u11279j
73 m pd78052(a), 78053(a), 78054(a) [memo]
74 m pd78052(a), 78053(a), 78054(a) notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
75 m pd78052(a), 78053(a), 78054(a) nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 8
m pd78052(a), 78053(a), 78054(a) the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. fip and iebus are trademarks of nec corporation. ms-dos and windows are trademarks of microsoft corporation. ibm dos, pc/at, and pc dos are trademarks of international business machines corporation. hp9000 series 300, hp9000 series 700, and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc. news and news-os are trademarks of sony corporation. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5

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